FinFETs (fin field effect transistors) are non-planar field effect transistors. A fin is a thin segment of semiconductor material standing on edge, thereby making available multiple surfaces for the formation of gate structures. The fins have first and second major surfaces that are opposite one another and usually are symmetric about a center plane that bisects the fin lengthwise. The major surfaces are often illustrated as being parallel as in U.S. Pat. No. 7,612,405 B2 or Pub. No. US2008/0128797 A1, which are incorporated herein by reference; but process limitations usually result in surfaces that slope outwardly from top to bottom of the fin with the result that the cross-section of the fin is trapezoidal in shape. In some cases, the two major surfaces meet at the top. In some embodiments, a separate gate structure may be located on each surface of each fin. In other embodiments, there is a common gate structure for all surfaces.
Doped source and drain regions are located on opposite sides of the gates. As in a planar FET, a voltage applied to the gate controls current flow in the channel that extends between the source and drain regions in the semiconductor beneath the gate.
Typically, finFETs are extremely small. Fin heights are usually on the order of tens of nanometers (nm.).
Unfortunately, the extremely small dimensions of typical finFET devices make the devices susceptible to single event upsets (SEUs) (sometimes also referred to as soft error upsets) and electronic noise signals. SEUs may be caused by radiation that generates electron-hole pairs at a sensitive node within a cell. The operation and performance of an integrated circuit may be substantially compromised by such SEUs. For example, field programmable gate arrays (FPGAs) and other programmable logic devices (PLDs) may be particularly sensitive to SEUs occurring in configuration random access memory (CRAM) cells. Other types of integrated circuits, such as microprocessors and application specific integrated circuits (ASICS), may also be sensitive to SEUs.
In addition, finFET devices are also susceptible to electronic noise signals which may be transmitted by way of conductive paths from other parts of an integrated circuit. In particular, substrate noise may adversely impact the performance of a finFET device used in an analog circuit application.